RMII port

rmii_port.vhdl module is a bridge between ethernet MAC IPs with MII interface and RMII PHYs.

Notes

RMII clock (input) is a primary clock for module and all signals.

MII clock produced by module should be routed to dedicated clock network or used for clocking limited amount of logic elements for avoiding clock distribution problems.

There exist two variations of RMII PHY modules - with 50MHz reference clock output or with 25Mhz. This module assumes that this clock is 50Mhz one. For 25Mhz case you may use 2x clock multiplier.

For 10Mbit/s operation you have to use clock divider for providing 5Mhz as rmii_clk

This page was last modified on 7 Feb 2019